An Efficient Architecture Design for Deblocking Loop Filter

In this paper, an efficient VLSI architecture proper for adaptive deblocking loop filter in both H.264 and AVS is presented. In this architecture, data access is carefully organized and some other measures are adopted, all that facilitate pipelining in this architecture so as to increase the efficiency of getting data from the SRAM and highly reduce the total cycles of filtering process. This design supports both horizontal filtering and vertical filtering on the same circuit (a parallel-in parallel-out reconfigurable FIR filter). Experiment results show that only 236 clock cycles are needed to finish filtering a macroblock for deblocking filter in H.264, 272 for the one in AVS, and the synthesized logic gate count is only 13.5K and 12.2K (not include SRAM) respectively in H.264 and AVS under 0.18 m μ technology when the maximum frequency is 100 MHz.